Submission Deadline: April 12, 2017 - Extended
Submissions could be for full papers, short papers, poster papers, or posters
July 17 – July 21, 2017
SCOPE AND OBJECTIVES
Reconfigurable Systems (RS) and Networks on Chips (NoC) are increasingly finding use in applications that require high-performance computing (HPC), power-efficiency, or both. Field-Programmable Gate Arrays (FPGAs) are seeing adoption in mainstream for both big-data and big-compute applications. The use of NoCs - as opposed to conventional bus-based communication architectures - is already established in a variety of architectures.
While there is considerable maturity in the area of NoC and RS architectures, there is that familiar gap between the capability of such architectures, and the capability of programmers, compilers, and runtime systems to efficiently exploit the performance and efficiency dividends these architectures promise.
More specifically, the challenges -- and the corresponding opportunity for innovation -- can be broken down into four broad categories: programming, compilers, run-time infrastructures, and the architectures themselves. Wider adoption, especially of reconfigurable systems, is contingent on a synergetic development and maturity across these areas. Lack of such a synergy has been a major hurdle to RS and specifically FPGAs becoming more mainstream, but there are very strong indicators in the academia and the industry that this is changing. High Performance Reconfigurable Computing (HPRC) is specially getting widespread interest.
DRSN 2017 workshop is intended to serve as a forum and bring together researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of reconfigurable systems and NoCs in high-performance and/or power-efficient systems. The challenges to wider adoption of these technologies, arising out of programming environments, compilers, and runtime systems are of special interest to this workshop, along with innovations at the architectural level.
The DRNS Workshop topics of interest include (but are not limited to) the following:
Compilation, Programming Languages, and Domain-Specific Languages for HPRC
Tools, Frameworks, Design-flows for developing high-performance reconfigurable systems
Virtual Machines, Middleware, Run-time and Operating Systems
Applications of FPGAs and RS, including big-data and big-compute applications
Heterogeneous high performance computing
High-level and pure software programming for reconfigurable computing architectures
Tools for design space exploration of reconfigurable systems and NoC-based systems
Benchmarks: Compute performance and/or power and cost efficiency for cloud/HPC with reconfigurable architectures using FPGAs
Novel NoC Architectures for high-performance systems
Systems software support for advanced NoC-based systems
NoC-aware compilation and runtime systems
Reliability, scalability, availability, and fault tolerance
Area, energy, and performance evaluation
Case studies and FPGA-based implementation of reconfigurable systems and NoC-based systems
Mapping and scheduling of tasks onto NoC-based systems
Self-reconfiguration and self-optimization for HPC
Reconfigurable computing education
INSTRUCTIONS FOR PAPER SUBMISSIONS
You are invited to submit original and unpublished research works on above and other topics related to dynamic reconfigurable systems and networks. Submitted papers must not have been published or simultaneously submitted elsewhere. For Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. Short papers (up to 4 pages), poster papers and posters (please refer to http://hpcs2017.cisedu.info/1-call-for-papers-and-participation/call-for-posters for posters submission details) will also be considered. Please specify the type of submission you have. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments.
Submit a PDF copy of your full manuscript to the workshop paper submission site at https://cmt3.research.microsoft.com/DRSN2017. Acknowledgement will be sent within 48 hours of submission.
Only PDF files will be accepted, uploaded to the submission link above. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, significance, technical clarity and presentation, language, and references. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. At least one of the authors of each accepted paper will have to register and attend the HPCS 2017 conference to present the paper at the workshop.
Accepted papers will be published in the Conference proceedings. Instructions for final manuscript format and requirements will be posted on the HPCS 2017 Conference web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is projected to be included in the IEEE or ACM Digital Library and indexed in all major indexing services accordingly.
Plans are underway to have the best papers, in extended version, selected for possible publication in a journal as special issue. Detailed information will soon be announced and will be made available on the conference website.
If you have any questions about paper submission or the workshop, please contact the workshop organizers.
Paper Submissions: ------------------------------------------- April 12, 2017 - Extended
Acceptance Notification: -------------------------------------- April 28, 2017
Camera Ready Papers and Registration Due by: ----------- May 11, 2017
Conference Dates: -------------------------------------------- July 17 – 21, 2017
Institut für Technik der Informationsverarbeitung (ITIV)
Karlsruhe Institute of Technology - KIT
Engesserstraße 5, Building 30.10, 76131 Karlsruhe, Germany
Phone: +49 721 608-42502
Fax: +49 721 608-42925
Institut für Informatik, TU Clausthal
Julius-Albert-Str. 4, Raum 210, 38678 Clausthal-Zellerfeld, Germany
International Program Committee*:
All submitted papers will be rigorously reviewed by the workshop technical program committee members following similar criteria used in HPCS 2017 and will be published as part of the HPCS 2017 Proceedings.
Falco Bapp, Karlsruhe Institute of Technology (KIT), Germany
Masoud Daneshtalab, KTH Royal Institute of Technology, Sweden
Umut Durak, German Aerospace Center (DLR), Germany
Miriam Leeser, Northeastern University, Massachusetts, USA
Jari Nurmi, Tampere University of Technology, Finland
Muhammad Adeel Pasha, Lahore University of Management Science (LUMS), Pakistan
Thilo Pionteck, University of Lübeck, Germany
Sai Rahul Chalamalasetti, Hewlett-Packard Labs, California, USA
Andreas Reinhardt, TU Clausthal, Germany
Aaron Smith, Microsoft Research, Redmond, Washington, USA
Dirk Stroobandt, Ghent University, Belgium
Zain Ul-Abdin, Halmstad University, Sweden
Nikos Voros, Technological Educational Institute of Western Greece (TWG), Greece
Syed Waqar Nabi, University of Glasgow, U.K.
(* Committee formation is pending and will be finalized shortly.)
For information or questions about Conference's paper submission, tutorials, posters, workshops, special sessions, exhibits, demos, panels and forums organization, doctoral colloquium, and any other information about the conference location, registration, paper formatting, etc., please consult the Conference’s web site at URL: http://hpcs2017.cisedu.info or http://cisedu.us/rp/hpcs17 or contact one of the Conference's organizers.